1. Technical Field
This disclosure generally relates to computer systems, and more specifically relates to high-speed serial communication interfaces.
2. Background Art
Some processors use high-speed serial communication interfaces for on-chip communications. In some interfaces, each packet is acknowledged using an ACK (acknowledge) message when the packet is correctly received, and a NACK (negative acknowledge) message when the packet is not received or is incorrectly received. In synchronous interfaces that run off the same clock, it is possible to use a single-bit ACK by training the transceivers on both sides of an interface, during which the transceivers count the cycles from transmitting a packet to getting the ACK bit for the packet. When both transceivers run on the same clock, the number of cycles from transmitting a packet to receiving the ACK bit for the packet is a constant and does not change. The use of single-bit ACKs to acknowledge receipt of a packet is a very efficient way to verify the receipt of packets in a serial communication interface.
When transceivers that communicate with each other run on different clocks, the number of cycles from transmitting a packet to receiving the ACK bit for the packet is no longer constant, but may change due to the mismatch between clocks, even when the clocks are supposedly the same speed. Even a slight difference in clock speed can lead to drift that can cause the number of cycles between transmitting a packet and receiving an ACK bit for the packet to change. Thus, when different clocks are used for two transceivers, the known ways of acknowledging packets using a single-bit ACK will not work.